A Pipelined Multi-core MIPS Machine

Hardware Implementation and Correctness Proof

Nonfiction, Computers, Programming, Software Development, General Computing
Cover of the book A Pipelined Multi-core MIPS Machine by Mikhail Kovalev, Silvia M. Müller, Wolfgang J. Paul, Springer International Publishing
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Author: Mikhail Kovalev, Silvia M. Müller, Wolfgang J. Paul ISBN: 9783319139067
Publisher: Springer International Publishing Publication: November 24, 2014
Imprint: Springer Language: English
Author: Mikhail Kovalev, Silvia M. Müller, Wolfgang J. Paul
ISBN: 9783319139067
Publisher: Springer International Publishing
Publication: November 24, 2014
Imprint: Springer
Language: English

This monograph is based on the third author's lectures on computer architecture, given in the summer semester 2013 at Saarland University, Germany. It contains a gate level construction of a multi-core machine with pipelined MIPS processor cores and a sequentially consistent shared memory.

The book contains the first correctness proofs for both the gate level implementation of a multi-core processor and also of a cache based sequentially consistent shared memory. This opens the way to the formal verification of synthesizable hardware for multi-core processors in the future.

Constructions are in a gate level hardware model and thus deterministic. In contrast the reference models against which correctness is shown are nondeterministic. The development of the additional machinery for these proofs and the correctness proof of the shared memory at the gate level are the main technical contributions of this work.

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This monograph is based on the third author's lectures on computer architecture, given in the summer semester 2013 at Saarland University, Germany. It contains a gate level construction of a multi-core machine with pipelined MIPS processor cores and a sequentially consistent shared memory.

The book contains the first correctness proofs for both the gate level implementation of a multi-core processor and also of a cache based sequentially consistent shared memory. This opens the way to the formal verification of synthesizable hardware for multi-core processors in the future.

Constructions are in a gate level hardware model and thus deterministic. In contrast the reference models against which correctness is shown are nondeterministic. The development of the additional machinery for these proofs and the correctness proof of the shared memory at the gate level are the main technical contributions of this work.

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