Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs

Nonfiction, Science & Nature, Technology, Electronics, Circuits, Computers, Advanced Computing, Engineering, Computer Architecture
Cover of the book Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs by Brandon Noia, Krishnendu Chakrabarty, Springer International Publishing
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Author: Brandon Noia, Krishnendu Chakrabarty ISBN: 9783319023786
Publisher: Springer International Publishing Publication: November 19, 2013
Imprint: Springer Language: English
Author: Brandon Noia, Krishnendu Chakrabarty
ISBN: 9783319023786
Publisher: Springer International Publishing
Publication: November 19, 2013
Imprint: Springer
Language: English

This book describes innovative techniques to address the testing needs of 3D stacked integrated circuits (ICs) that utilize through-silicon-vias (TSVs) as vertical interconnects. The authors identify the key challenges facing 3D IC testing and present results that have emerged from cutting-edge research in this domain. Coverage includes topics ranging from die-level wrappers, self-test circuits, and TSV probing to test-architecture design, test scheduling, and optimization. Readers will benefit from an in-depth look at test-technology solutions that are needed to make 3D ICs a reality and commercially viable.

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This book describes innovative techniques to address the testing needs of 3D stacked integrated circuits (ICs) that utilize through-silicon-vias (TSVs) as vertical interconnects. The authors identify the key challenges facing 3D IC testing and present results that have emerged from cutting-edge research in this domain. Coverage includes topics ranging from die-level wrappers, self-test circuits, and TSV probing to test-architecture design, test scheduling, and optimization. Readers will benefit from an in-depth look at test-technology solutions that are needed to make 3D ICs a reality and commercially viable.

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