iRODS Primer 2

Integrated Rule-Oriented Data System

Nonfiction, Computers, Database Management, Information Storage & Retrievel, Reference & Language, Language Arts, Library & Information Services
Cover of the book iRODS Primer 2 by Yu-ting Chen, Jason Cong, Michael Gill, Glenn Reinman, Bingjun Xiao, Zhiyang Ong, Morgan & Claypool Publishers
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Author: Yu-ting Chen, Jason Cong, Michael Gill, Glenn Reinman, Bingjun Xiao, Zhiyang Ong ISBN: 9781627059725
Publisher: Morgan & Claypool Publishers Publication: July 1, 2015
Imprint: Morgan & Claypool Publishers Language: English
Author: Yu-ting Chen, Jason Cong, Michael Gill, Glenn Reinman, Bingjun Xiao, Zhiyang Ong
ISBN: 9781627059725
Publisher: Morgan & Claypool Publishers
Publication: July 1, 2015
Imprint: Morgan & Claypool Publishers
Language: English
Since the end of Dennard scaling in the early 2000s, improving the energy efficiency of computation has been the main concern of the research community and industry. The large energy efficiency gap between general-purpose processors and application-specific integrated circuits (ASICs) motivates the exploration of customizable architectures, where one can adapt the architecture to the workload. In this Synthesis lecture, we present an overview and introduction of the recent developments on energy-efficient customizable architectures, including customizable cores and accelerators, on-chip memory customization, and interconnect optimization. In addition to a discussion of the general techniques and classification of different approaches used in each area, we also highlight and illustrate some of the most successful design examples in each category and discuss their impact on performance and energy efficiency. We hope that this work captures the state-of-the-art research and development on customizable architectures and serves as a useful reference basis for further research, design, and implementation for large-scale deployment in future computing systems.
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Since the end of Dennard scaling in the early 2000s, improving the energy efficiency of computation has been the main concern of the research community and industry. The large energy efficiency gap between general-purpose processors and application-specific integrated circuits (ASICs) motivates the exploration of customizable architectures, where one can adapt the architecture to the workload. In this Synthesis lecture, we present an overview and introduction of the recent developments on energy-efficient customizable architectures, including customizable cores and accelerators, on-chip memory customization, and interconnect optimization. In addition to a discussion of the general techniques and classification of different approaches used in each area, we also highlight and illustrate some of the most successful design examples in each category and discuss their impact on performance and energy efficiency. We hope that this work captures the state-of-the-art research and development on customizable architectures and serves as a useful reference basis for further research, design, and implementation for large-scale deployment in future computing systems.

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