Low-Power Variation-Tolerant Design in Nanometer Silicon

Nonfiction, Science & Nature, Technology, Electronics, Circuits, Computers, Application Software, CAD/CAM
Cover of the book Low-Power Variation-Tolerant Design in Nanometer Silicon by , Springer US
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Author: ISBN: 9781441974181
Publisher: Springer US Publication: November 10, 2010
Imprint: Springer Language: English
Author:
ISBN: 9781441974181
Publisher: Springer US
Publication: November 10, 2010
Imprint: Springer
Language: English

Design considerations for low-power operations and robustness with respect to variations typically impose contradictory requirements. Low-power design techniques such as voltage scaling, dual-threshold assignment and gate sizing can have large negative impact on parametric yield under process variations. This book focuses on circuit/architectural design techniques for achieving low power operation under parameter variations. We consider both logic and memory design aspects and cover modeling and analysis, as well as design methodology to achieve simultaneously low power and variation tolerance, while minimizing design overhead. This book will discuss current industrial practices and emerging challenges at future technology nodes.

View on Amazon View on AbeBooks View on Kobo View on B.Depository View on eBay View on Walmart

Design considerations for low-power operations and robustness with respect to variations typically impose contradictory requirements. Low-power design techniques such as voltage scaling, dual-threshold assignment and gate sizing can have large negative impact on parametric yield under process variations. This book focuses on circuit/architectural design techniques for achieving low power operation under parameter variations. We consider both logic and memory design aspects and cover modeling and analysis, as well as design methodology to achieve simultaneously low power and variation tolerance, while minimizing design overhead. This book will discuss current industrial practices and emerging challenges at future technology nodes.

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